4.1 Central Processing Unit Architecture 中央处理器体系结构

Syllabus learning goals 考纲学习目标

完成本节后，学生需要能够：

• 解释 basic Von Neumann model 和 stored program concept。
• 说明 general-purpose 与 special-purpose registers 的区别及各寄存器作用。
• 说明 ALU、CU、system clock 和 IAS 的作用。
• 解释 address、data、control buses 如何传输信息。
• 解释 processor type/cores、bus width、clock speed 和 cache 如何影响 performance。
• 为 peripheral device 选择 USB、HDMI 或 VGA port。
• 使用 register-transfer notation 描述 Fetch–Execute cycle。
• 解释 interrupts 的原因、检测时间和 ISR 处理过程。

本节简答题最常见的失分原因是把 “address” 与 “data/instruction” 混用。PC/MAR 保存 address；MDR/CIR/ACC 保存 data、instruction 或 result。

1 Von Neumann model and stored program concept

Basic Von Neumann model 包含 CPU、Immediate Access Store、input/output 和连接它们的 buses。CPU 内包含 Control Unit、ALU 和 registers。

Stored program concept 的标准定义：

Instructions and data are stored in the same memory space / main memory.

程序 instructions 以 binary 形式保存在 memory 中，与 data 一样按 address 取出。CPU 重复执行 Fetch–Decode–Execute cycle。

2 Registers 寄存器

Register 是 CPU 内部容量很小、访问速度很快的 storage location。

• General-purpose register 可由多种 instructions 使用，保存 data 或 intermediate result。
• Special-purpose register 在处理器工作过程中承担固定角色。

Special-purpose registers

Common corrections

• PC 不保存 “the next instruction”；它保存 the address of the next instruction。
• MAR 不保存 data；它保存 memory address。
• MDR 不负责决定 address；它保存从 MAR 指定位置读出或将写入该位置的 data/instruction。
• CIR 保存当前正在 decode/execute 的 instruction，而不是下一个 instruction 的 address。

3 ALU, CU, system clock and IAS

Arithmetic and Logic Unit (ALU)

• Performs arithmetic operations，例如 addition、subtraction、increment。
• Performs logical operations，例如 AND、OR、XOR、comparisons 和 shifts。
• Results 通常暂存在 ACC，并可能更新 Status Register flags。

Control Unit (CU)

• Coordinates and manages execution of instructions。
• Decodes the instruction in CIR。
• Sends and receives control signals。
• Initiates transfers between registers, memory, ALU and input/output devices。

System clock

• Generates regular timing signals。
• Timing signals travel on the control bus。
• Synchronises operations so components perform actions in the correct sequence。

Immediate Access Store (IAS)

• Holds instructions, programs and data currently in use。
• Has fast access time。
• Is volatile, so contents are lost when power is removed。

IAS 在本考纲语境中就是 CPU 可快速访问的 primary/main memory，不要把它写成 secondary storage。

4 System buses

Data transfer example: memory read

• MAR places the required address on the address bus。
• CU sends a memory-read signal on the control bus。
• Memory finds the location and places its contents on the data bus。
• The value enters MDR。

Memory write

• MAR contains the destination address and sends it on the address bus。
• MDR contains the data and sends it on the data bus。
• CU sends a memory-write signal on the control bus。
• Memory stores the data at the specified address。

Clock and CU together

The system clock generates timing signals. These travel on the control bus and synchronise components. The CU generates control signals on the control bus and initiates the required data transfers.

5 Factors affecting performance

Explain 题必须写 feature → hardware effect → performance result。

Processor type and number of cores

• More cores can execute more instructions/processes concurrently when software supports parallel processing。
• A suitable processor architecture may execute instructions more efficiently or provide specialised operations。

Limitations：

• Not all software is designed to use multiple cores, so additional cores may remain idle。
• Cores need to communicate/synchronise, which can increase latency。
• Poor coordination can create waiting or deadlock situations。
• More cores can generate more heat and consume more power。

Clock speed

A higher clock speed allows more Fetch–Execute cycles per second, so more instructions/data can be processed each second.

Higher clock speed may also increase heat and power consumption；不能只写 “higher GHz is faster”。

Bus width

• Wider data bus transfers more bits at the same time, reducing the number of transfers required。
• Wider address bus can represent more addresses, increasing maximum addressable memory。

题目若问 performance，优先解释 data bus width；address bus width 主要影响 addressable memory capacity。

Cache memory

Cache 使用 fast SRAM，保存 frequently/recently used instructions and data，位置接近或位于 CPU。

A larger cache can hold more frequently used instructions/data, reducing accesses to slower RAM, so the CPU spends less time waiting.

Cache 不是额外 CPU core，也不永久保存文件。

6 Ports and peripheral connections

USB

• General-purpose serial connection for many peripherals。
• Can transfer data and may supply power。
• Supports plug-and-play：connection causes a detectable voltage/device change；the OS identifies the device and loads the appropriate driver。
• Suitable for removable solid-state drives、printers、external optical drives and some VR devices。

HDMI

• Digital interface carrying high-resolution video and audio on one cable。
• Higher transfer rate than VGA and supports modern high-resolution displays。
• No separate audio cable is required for monitor speakers。
• Digital transfer avoids digital-to-analogue conversion and is less prone to analogue interference/crosstalk。

VGA

• Carries analogue video only。
• Does not carry audio；a separate audio cable is needed。
• More susceptible to signal degradation/interference and less suitable for high-resolution digital displays。

Choice pattern

Use HDMI for the monitor because it carries digital high-resolution video and audio through one cable. Use USB for the storage device because it is a common data interface and supports automatic device detection and driver loading.

7 Fetch–Execute cycle

Register-transfer notation

MAR ← [PC]
PC  ← [PC] + 1
MDR ← [[MAR]]
CIR ← [MDR]

Notation：

• [PC] means the contents of PC。
• MAR ← [PC] means copy the contents of PC into MAR。
• [[MAR]] means the contents of the memory location whose address is stored in MAR。
• Arrow ← means the value on the right is copied to the location on the left。

Fetch stage

• MAR ← [PC]：copy the address of the next instruction into MAR。
• PC ← [PC] + 1：increment PC so it points to the following instruction。
• MDR ← [[MAR]]：read the instruction from the memory address in MAR into MDR。
• CIR ← [MDR]：copy the fetched instruction into CIR。

Decode and execute

• CU decodes the opcode and operand in CIR。
• CU sends control signals to move data or select the required operation。
• ALU/registers/memory/I/O execute the instruction。
• Results may be stored in ACC, another register or memory；Status Register may be updated。

Register transfers must be in the correct order。特别注意 PC increment 通常与 address 已复制到 MAR 后发生，因此不会丢失当前 instruction address。

8 Interrupts

Interrupt 是需要 CPU attention 的 signal/event，使 CPU 暂停正常程序并执行 Interrupt Service Routine (ISR)。它避免 CPU 不断 polling 每个设备。

Causes

Hardware causes：

• Key pressed / input device event。
• Printer or storage buffer empty/full or operation completed。
• Timer signal。
• Hardware fault or power event。

Software causes：

• Division by zero or runtime error。
• Out-of-memory-bounds access。
• Program requests an external device/input。
• Buffer overflow。

When detected

Interrupt flags are checked after the execute stage / at the end of each Fetch–Execute cycle, before the next cycle begins.

这样避免在一条 instruction 执行到一半时破坏 processor state。

Interrupt handling sequence

• CPU checks whether an interrupt flag is set。
• It compares interrupt priority with the task/interrupt currently being handled。
• If priority is high enough, it temporarily disables or masks lower-priority interrupts。
• It saves current register contents/processor state, including the return address。
• It identifies the interrupt source。
• The address of the appropriate ISR is loaded into PC。
• ISR services the device/event and clears the interrupt condition/flag。
• Saved registers and return address are restored。
• Lower-priority interrupts are re-enabled and the interrupted program resumes。

Why save registers

The original program must continue from the same state after the ISR。若 ACC、PC、Status Register 等没有保存，ISR 改变它们后，原程序的 result、condition 或 next instruction 都可能错误。

9 Exam-answer checklist 真题检查表

• Stored program concept 是否写 instructions and data in the same memory？
• PC/MAR 是否明确写 address，MDR/CIR 是否明确写 data/instruction？
• CU 是否写 control signals/coordination，clock 是否写 timing/synchronisation？
• 三条 bus 是否分别对应 address、data、control signals？
• Performance answer 是否形成 feature → hardware effect → result？
• HDMI 是否写 digital video + audio，USB 是否写 device detection/driver？
• Fetch stage 是否按正确顺序写四条 transfer notation？
• 是否理解 [MAR] 与 [[MAR]] 的区别？
• Interrupt 是否写在 execute 后检测？
• ISR 过程是否包含 save state、load ISR address、restore state、resume？

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本材料依据 9618 syllabus 4.1 的八项要求，并综合本页所列 2021-2025 past-paper questions 及 mark schemes。加粗英文表达优先采用评分方案中反复出现的得分用词。